Khadeer Ahmed

PhD

R & D Engineer, Senior I
Synopsys, Inc
690 East Middlefield Road
Mountain View, CA 94043

Email: khahmed [at] syr [dot] edu

Adviser: Dr. Qinru Qiu
Department of Electrical Engineering and Computer Science
Syracuse University
4-226 Center for Science and Technology
Syracuse, NY 13244

Education


PhD in Electrical & Computer Engineering
Syracuse University, Syracuse, NY

Masters of Science in Computer Engineering
Syracuse University, Syracuse, NY

Bachelor of Engineering in Electronics and Communication
R.N.S. Institute of Technology, Bangalore, India

Research Interests


  • Neuromorphic computing
  • High performance computing for brain inspired applications
  • Spiking neural networks
  • Large scale simulation of spiking neural networks

Honors and Awards


  • Outstanding Achievement Award in Graduate Studies computer engineering at Syracuse University
  • Best Out-Going Meritorious Student of Electronics and Communication Engineering, RNSIT, Bangalore
  • 1st place in technical presentation in intra college fest
  • 2nd place in circuit debugging event in inter college National level technical event
  • Secured 91 percentile in the National IT Aptitude Test 2005

Work Experience


Synopsys

R & D Engineer, Senior I [Jul 2017 to present]

  • Perform research and development of static timing analysis and sign off tool, PrimeTime
IBM

Training [Aug 2015, May 2016]

  • Comprehensive training on TrueNorth neurosynaptic processor for implementing spiking neural networks

Research collaboration

  • Implementation of inference based confabulation model using recurrent spiking neural networks on IBM TrueNorth neurosynaptic processor
Intel

Intern [Jan 2013 to Jul 2013]

  • Optimized and implemented pattern matching algorithm, Brain-State-in-a-Box (BSB) on Intel Xeon Phi coprocessor

Research collaboration

  • Optimization and distributed implementation of Intelligent Text Recognition System on Intel Xeon Phi coprocessors
Syracuse University

Research Assistant [Jan 2012 to July 2017]

  • Document Image Parsing and Understanding using Neuromorphic Architecture
  • High performance computing with distributed implementations on heterogeneous clusters
  • High performance simulation of spiking neural networks
  • Low power spiking neural network implementation using IBM TrueNorth neurosynaptic processor
  • Hardware spiking neuron architectures and implementation
  • Surface EMG signal processing and simulation
  • Researched building a system that is immune to malware

Teaching Assistant

  • Object Oriented Design course [CSE 687 - Spring 2010], [CSE 283 - Fall 2011]
iWave Systems

Member Technical – Hardware [May 2007 to Jul 2008]

  • Developed and maintained Storage IP cores for FPGA (CE-ATA, MMC, SD, SDIO, NAND Flash)
  • Developed RTL using Verilog along with preparation of Design, Test Plan and Test case documents.
  • Developed diagnostic code to assist driver development.

Activities/Affiliations


  • GROVE (Group of VLSI Enthusiasts), Syracuse University President (2010-2011)
  • Was a volunteer at Aashayein Foundation which empowers under privileged children with education
  • Institute of Electrical and Electronics Engineers (IEEE) member
  • Phi Beta Delta. Honor society dedicated to International Scholarship [Invited Membership]
  • Recognised by Marquis Who's Who for achivements in Electronics Engineering [Press Release]